The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, when fabricating field effect transistors (FETs), such as fin-like FETs (FinFETs), device performance can be improved by using a high-k metal gate instead of a typically polysilicon gate. Work function of a high-k metal gate can be tuned by selecting materials and thickness of certain work function metal layer(s) in the high-k metal gate. As FET devices continue scaling down, lower threshold voltage (Vt) in gate terminals (directly related to work function thereof) is desired in order to further speed up the operation of the FET devices. However, it has been difficult to continually lower the work function of existing high-k metal gates, particularly for n-type FETs (or NFETs), due to the consideration of gate stack engineering and fabrication. For example, in order to reduce the interaction between a high-k dielectric layer and a work function metal layer, a barrier layer is typically placed between them. This barrier layer sometimes increases the work function of the metal gate.